1. Field of the Invention
The invention relates in general to a mother-board, and more particularly to a mother-board having multiple PCI Express X16 graphics interfaces.
2. Description of the Related Art
Computer bus specifications have been developed from the ISA architecture (16 bit@8.33 Mhz) of the 1980 years to the PCI architecture (32 bit@33 Mhz) of the 1990 years and to the current AGP architecture (32 bit@66 Mhz). In the current peripheral interface card, particularly the graphics card (or display card), however, the data transmission amount thereof is getting more and more insufficient under the transmission architecture of the bus AGP. So, a new PCI Express bus specification has been proposed. The PCI Express utilizes the switch type peer-to-peer sequence transmission technology. The data transmission of the PCI Express utilizes a transmitter (Tx) and a receiver (Rx), which constitute a simplex lane. Each PCI Express individually utilizes its own lane to communicate with the corresponding chipset on the mother-board, and the bus-sharing architecture of the conventional PCI is no longer used.
The current transmission speed in the PCI Express single lane may reach 250 MB/s, and the occasion in the single lane is referred to as the PCI Express x1 (one lane) having a transmission bandwidth of 1×250=250 MB/s. In order to cover the transmission bandwidth requirements in various level fields, the current PCI Express has various specifications of x1, x2, x4, x8, x16, x32, and the like. Different specifications correspond to different foot piece designs, and thus have different physical lengths. The transmission bandwidth between the mother-board chipset and the graphics interface starts from the PCI Express x16 specification to 4 GB/s, which is sixteen times that of the PCI Express x1 and approaches twice of the current AGP X8 of 2.1 GB/s. The PCI Express also can operate in the full duplex mode. The PCI Express has a pair of two sets of specific transmitters and receivers. Each of the sets of specific transmitters and receivers only performs the one-way transmission, so the speed may be doubled. So, in the full duplex PCI Express x16 specification, the transmission bandwidth may reach 8 GB/s.
FIG. 1 is a schematic illustration showing the connection architecture of a conventional PCI Express x16 graphics interface. In the specification of the PCI Express x16 graphics interface 104, the transmission bandwidth may reach 8 GB/s. So, in the normal condition, all of the 16 lanes of the chipset 102 are connected to the only PCI Express x16 graphics interface 104. So, when the x16 graphics card (not shown in FIG. 1) is inserted into the PCI Express x16 graphics interface 104, the system operates in the x16 mode, and may utilize the transmission bandwidth of 8 GB/s ideally. However, the current x16 graphics card only can utilize the transmission bandwidth of about 4 GB/s, and the transmission bandwidth of the residual 4 GB/s is not utilized. Thus, the cost efficiency cannot be satisfied. As a result, it is an important subject in the industry to optimize the high transmission bandwidth provided by the PCI Express x16 graphics interface 104 and sufficiently increase the system display efficiency without wasting the redundant transmission bandwidth.